Hello,
I am writing a Verilog checker, which has to be activated only when, a signal, say “signal_a” is stable for 2(fixed number of clocks) clocks. Here, I am not writing a System verilog assertion, as the complexity of my check constrains me to write a checker, which would make it simpler and easier to edit.
Thanks.
In reply to mayurkubavat:
No…I know that…I have used a code for checking the stability of a signal for 2 consecutive clocks, which is:
always @(posedge clk)
begin
first_cycle = a;
@(posedge clk);
second_cycle = a;
end
always @(posedge clk)
begin
if(first_cycle == second_cycle)
begin
out = 0;
out_a = first_cycle;
end
else
out = 1;
end
////////////
Now, based on “out” value I will enable or disable my checker.
//////////////
In reply to Saraswati:
I don’t think the checker would work always. Since there are two always blocks sensitive to posedge clk, there are chances of race conditions here.
Also since you are checking the stability of signal a, what if signal a has a glitch in between the two posedges of clk. The checker would miss it and will still say signal a is stable.
So, I would suggest instead of checking @(posedge clk), you can perform checks at every change in the signal itself.
Eg.
. . .
time signal_change_time = 0;
time clk_period;
always@(posedge signal_a or negedge signal_a)
begin
signal_change_time = $time - signal_change_time;
if(signal_change_time <= 2 * clk_period)
out = statement 1;
else
out = statement 2;
end
. . .