Verilog case statment

SystemVerilog
,
1 
input [1:0] dll_speed_mode
real MIN_FREQ , MAX_FREQ
always @(*)
     begin
        case (dll_speed_mode)
          2'b00:
            begin
               MIN_FREQ       = 100;
               MAX_FREQ       = 180;
               
            end
          2'b01:
            begin
               MIN_FREQ       = 180;
               MAX_FREQ       = 266;
               
            end
          2'b10:
            begin
               MIN_FREQ       = 266;
               MAX_FREQ       = 333;
               
            end
          2'b11:
            begin
               MIN_FREQ       = 333;
               MAX_FREQ       = 400;
               
            end
          default:
            begin
               MIN_FREQ       = 160;
               MAX_FREQ       = 400;
               
            end
        endcase // case (dll_speed_mode)
     end

I have a question here and want to understand how case statment works

If my dll_speed_mode is 2’hx

Which case statement is excusted (is it default ?)
What will be the values of MIN_FREQ and MAX_REQ

Thanks,
Tejas

2

In reply to tejasakulu:

A case statement uses case equality (===) where x’s and z’s are included matching expressions. So if dll_speed_mode is 2’hx, the default branch is selected.

3

If you are expecting something different then review casez or casex statements in Section 12.5.1 of the latest SystemVerilog manual.

4

In reply to dave_59:

Hi Dave,

I understand this now:

However my waveform tells a different story

When dll_speed_mode is toggling from 2’hx to 2’h0 i get an error in questa sim

When dll_speed_mode is 2’hx MAX_FREQ is 0 and not 400

Can you tell me what is causing this

5

In reply to logie:

Hi Logie,

Its an RTL code, i cannot modify it without the designers permission

Thanks

6

In reply to tejasakulu:

Without knowing the details of the error, I am guessing that the
always @() has not been trigerred even once. Remember the always @()
will be evaluated only when dll_speed_mode goes through the first
transition. Till then the real values MIN and MAX_FREQ will be 0.

After the first transition to 2’b00, then the MIN and MAX_FREQ should be
100 and 180.

7

In reply to tejasakulu:

You need to tell us what the error is, and also explain how dll_speed_mode gets its value.

8

In reply to dave_59:

Thanks Dave.

In reply to logie:

Rightly said. Thanks Logie, I debuggged it, There was bug in the design - A candidate for race condition with multiple always block

Thanks for the pointers

Tejas