For any of those chip designers / verification engineers coding in Verilog or SystemVerilog, please check out my script. It’s the fastest and most accurate available (IMO).
The easiest way to install the script is to follow the README on the GitHub page.
In addition to syntax highlighting and indenting, you can also enable these additional features (if enabled via .vimrc):
matchit - Using shift-5 (%) to hop between starting and ending tokens
begin → end → begin
module → endmodule → module
( → ) → (
function → endfunction → function
and many other examples
folding - Using zc and zo to hide portions of text based on indented sections
Replacing tabs with spaces by re-indenting the complete file
To use systemverilog.vim you can visit the GitHub page:
This script is not OVM/UVM aware.
Feel free to share feedback. Thanks!