I'll be teaching a Verification course this spring; while I've done a fair amount of verification over the years, I'm certainly not a Systemverilog expert. So, a how-to question. (Note that this is in pure Systemverilog; not UVM).
My example is a 2D-mesh routing fabric. The fabric is made of mesh stops; each mesh stop is made of FIFOs (among other things). The verification environment should have a tracker that looks through the entire design hierarchy, finds packets (let say just in the FIFOs) and prints them. Can I do this in any way that doesn't require hard-coding the entire design hierarchy into the verification code?
I thought of using "bind my-fifo-module-name interf-type ports" to insert an interface object into every FIFO instance. The simulator would then find every FIFO instance for me, without my needing to know where they all are. But I can't quite figure out how to make this work:
- bind() doesn't return a list of all the instances it created, so my Tracker cannot query all the interface instances to find packets.
- the FIFOs are made of user code that doesn't even know it has had an interface object inserted, so they won't be able to go and register the interface objects with the Tracker.
- if the Interface object had,e.g., an always_comb block inside, it could react to any change in the FIFO internal memory and notify the Tracker. But while an Interface can contain functions and tasks, it cannot contain an "always_comb" block.
So I'm kind of stuck. Any ideas?