Vector assignment in system verilog

SystemVerilog
,
1

I defined a signal as

output logic [15:0]data;

what is the difference between the following assignments if mem[addr] is a 16 bit vector?

data[15:0] = mem[addr];

[15:0]data = mem[addr];
2

The second assignment is illegal. When assigning you can only specify array dimensions, packed or unpacked, at the right side of array name. If you ask about difference between

logic [15:0] data
logic data [15:0]

it is that dimensions specified before array name are “packed” dimensions which means that elements occupying these indexes are reliably positioned next to each other in memory. The dimensions specified after the array name are “unpacked” dimensions, which means those elements could be arranged in memory in a distributed way, as deemed optimal by the SV engine, not necessarily next to each other.