Variable_assertion

SystemVerilog
1

Having 3 signals
a,b,clk
initially
a=1
after 0.10ns
clock is started
2 clock pulse after clock started
b=1.

in same way at the end side of the signals
b=0
2clock pulse delay clock is stopped
after clock delay 0.10
a=0

can anyone suggest how it is possible???, i have tried with variable delay assertion but i am not able to make it.

2

In reply to hamza_9515:
I suggest that you use a task as described in my paper
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue

Below is a sample; your requirements are ambitious, but you can tune my approach as needed.

 
initial begin 
  fork
     t_ab();
  join_none
end
task automatic t_ab();
  repeat(2) @(posedge clk);
  assert (b==1'b1);
  //?? in same way at the end side of the signals
  wait(b==1'b0);
  repeat(2) @(posedge clk);
  assert (b==1'b0);
endtask

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
3

In reply to ben@SystemVerilog.us:

Thank you for reply.
But i am having clock signal which is activating after a=1.
a=1;
#0.10;
Clk=1;
always @clk=~clk;
#2;
b=1;

//At the end side
b=0;
#2;
Clk=0;
#0.10;// floting point delay between clk and a signal
a=0;

Clock is starting after a=1.
At the end side Clock is stopped after b=0.

How can I implement in task??
I understand that you are using repeat statement for delay (2).
But that floating point delay is there???.

4

In reply to hamza_9515:
Use a task as per my paper. A task gives you lots of
freedom in defining the sequence and tests.
You can use the wait(), Delay, immediate assert,
@posedge, if, other forks.
You need to understand your requirements and write the proper task, and when to
trigger the fork. You wanted guidance, and that is my recommendation.

 

task automatic t_ab();
// But i am having clock signal which is activating after a=1.
  wait(a==1);
  #0.10;
  assert(Clk==1);
  // always @clk=~clk;
  //?? Now clk is running forever? Then
  // use clk edges for the next tests
  repeat(2) @(posedge clk);
// also No concurrent assertions in tasks
  assert (b==1'b1);
  //?? in same way at the end side of the signals
  wait(b==1'b0);
  // repeat(2) @(posedge clk);
  #2;
  assert (b==1) ;
//At the end side
//? Meaning what? How test? wait (??)
  assert (b==0);
  #2;
  assert (Clk==0) ;
  #0.10;// floting point delay between clk and a signal
  assert (a==0) ;
  assert (b==1'b0);
endtask
5

[i]In reply to ben@SystemVerilog.us:[t

Thank you “Ben”
This is easy in terms of task.