Variable Transition Checker

SystemVerilog
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1

Hi All,

There is any direct method/mechanism to get transition of any variable in system verilog or UVM method…?

For Example, I have one variable :

bit [3:0] temp;

I want to generate event(START_TIMER) when temp variable value change 1 to 2.

Looking forward to your inputs on the same.

Regards,
Manoj

2

In reply to manoj_k86:

You can try writing SV property.

3

In reply to Naven8:

Hi,

But can i use SV property in my SV class.?
Please provide sample example.

4

There are several ways to do this depending on the types of transitions expected and sampling requirements. These assume no sampling clocks.


module top;
class A;
   bit [3:0] temp;
   task run;
      fork
	 forever #10 temp++;
	 begin // if you know the order
	    wait(temp==1);
	    $display("temp==1");
	    wait(temp==2);
	    $display("temp==2");
	 end
	 begin // if you don't know the order
	    bit [3:0] temp_last;
	    forever @(temp)
	      if (temp_last == 1 & temp == 2)
		begin
		   $display("1 -> 2");
		   break;
		end
	      else
		temp_last = temp;
	 end  
      join_any
      #1 disable fork;
   endtask
endclass

   A h;
   initial begin
      h = new;
      h.run();
   end
endmodule
5

In reply to dave_59:

Thanks Dave.