Variable delay in $past(sig_name, vari_delay) assertion

SystemVerilog
, ,
1

Is there any that I can pass variable delay in $past(sig_name, vari_delay). Below is my assertion.

property p1;
@(negedge clk)
$changed(o_c_500k) |->($past($fell(ADC_START),5)==1) && ($past($fell(ADC_START),4)==0);
endproperty

I need to pass 5 and 4 inside $past through variables.

I tried with

 sequence delay_seq(v_delay);
    logic [3:0] delay;
    (1,delay=v_delay) ##0 first_match((1,delay=delay-1) [*0:$] ##0 delay <=0);
  endsequence

$changed(o_c_500k) |->($past($fell(ADC_START),delay_seq(o_c_500k_count+1))==1) && ($past($fell(ADC_START),delay_seq(o_c_500k_count))==0);
Couldn’t succeed. Please help me with this.

2

In reply to Nandeesha:
As you know, the expressions in $past must be static; it cannot be a variable or a sequence.

$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

In your model, you seem to want to express something like

$changed(o_c_500k) |->($past($fell(ADC_START),var)==1) && 
                                     ($past($fell(ADC_START),var-1)==0);

// This is the wrong way to see or express an assertion.  The recommended approach is the 
// forward-looking.  Thus, instead of saying
// BAD STYLE:  If  some_sequence_of_events then some_events must have happened in the past. 
// BETTER STYLE:  If some_events then other events now or in the future 
// Something like
// Instead of
       $changed(o_c_500k) |->($past($fell(ADC_START),5)==1) && 
                                    ($past($fell(ADC_START),4)==0);
// DO THIS
  $fell(ADC_START) |->  strong(##1 $stable(ADC_START)  // (like your ",5" ",4"
                               ##[1:$] $changed(o_c_500k));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
3

In reply to ben@SystemVerilog.us:
In you need a var delay between $fell(ADC_START) and $changed(o_c_500k)
consider using my package at
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
Thus,


//   $fell(ADC_START) |->  strong(##1 $stable(ADC_START)  // (like your ",5" ",4"
//                               ##[1:$] $changed(o_c_500k));   
import sva_delay_repeat_range_pkg::*;
int d1=30;  // dynamic var set to 30
sequence my_sequence; 
  $changed(o_c_500k); 
endsequence 
$fell(ADC_START) |->  strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
                             ##0 q_dynamic_delay(d1) ##0 my_sequence);  
// OK too (the sequence is needed for other cases, see the package) 
$fell(ADC_START) |->  strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
                             ##0 q_dynamic_delay(d1) ##0 $changed(o_c_500k));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
4

In reply to ben@SystemVerilog.us:

In reply to Nandeesha:
As you know, the expressions in $past must be static; it cannot be a variable or a sequence.

$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

In your model, you seem to want to express something like

$changed(o_c_500k) |->($past($fell(ADC_START),var)==1) && 
($past($fell(ADC_START),var-1)==0);
// This is the wrong way to see or express an assertion.  The recommended approach is the 
// forward-looking.  Thus, instead of saying
// BAD STYLE:  If  some_sequence_of_events then some_events must have happened in the past. 
// BETTER STYLE:  If some_events then other events now or in the future 
// Something like
// Instead of
$changed(o_c_500k) |->($past($fell(ADC_START),5)==1) && 
($past($fell(ADC_START),4)==0);
// DO THIS
$fell(ADC_START) |->  strong(##1 $stable(ADC_START)  // (like your ",5" ",4"
##[1:$] $changed(o_c_500k));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Hi Ben, thanks for your solution.
From your solution below, I see you’re checking from 1 to infinite cycle($).
$fell(ADC_START) |-> strong(##1 stable(ADC_START) // (like your ",5" ",4" ##[1:] changed(o_c_500k)); But I need to check exactly after 'n' cycles. 'n' is through the register and has been randomized. It'll be keep on repeating in the loop. I can't check it from 1 to some cycles. And also, ‘n’ changes at negedge of the clock and ADC goes low at the posedge of the clock. So is there any way that I can sample at both the edges in the assertion. The $past works for only one value (i.e only if it’s hard coded).

5

In reply to Nandeesha:


import uvm_pkg::*; `include "uvm_macros.svh" 
import sva_delay_repeat_range_pkg::*;  // see above for package
module m; 
int n;  // dynamic var  
// If n changes at the negedge clk, and you want to save that value before the fell of start
  property P; 
    int v; 
    @(negedge clk) (1, , v=n) ##0 @(posedge clk)($fell(ADC_START)) |-> 
       // consequent also @(posedge clk) because of flow through 
       strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
              ##0 q_dynamic_delay(v) ##0 $changed(o_c_500k)); 
  ap_P: assert property(P);  
  always @(negedge clk) 
  if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");
....

Does this answer the requirements?

Ben SystemVerilog.us

6

In reply to ben@SystemVerilog.us:

In reply to Nandeesha:


import uvm_pkg::*; `include "uvm_macros.svh" 
import sva_delay_repeat_range_pkg::*;  // see above for package
module m; 
int n;  // dynamic var  
// If n changes at the negedge clk, and you want to save that value before the fell of start
property P; 
int v; 
@(negedge clk) (1, , v=n) ##0 @(posedge clk)($fell(ADC_START)) |-> 
// consequent also @(posedge clk) because of flow through 
strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
##0 q_dynamic_delay(v) ##0 $changed(o_c_500k)); 
ap_P: assert property(P);  
always @(negedge clk) 
if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");
....

Does this answer the requirements?
Ben SystemVerilog.us

Sorry, the o_c_500k changes at negedge of the clock. ‘n’ will be configured way before. Please ignore n.

7

In reply to Nandeesha:

In reply to ben@SystemVerilog.us:
Sorry, the o_c_500k changes at negedge of the clock. ‘n’ will be configured way before. Please ignore n.

o_c_500k changes at negedge of the clock and ADC_START goes low at the posedge of the clock. Since I couldn’t attach the timing diagram here, I have emailed it you your email ID. Please see you email for further clarification. Sorry for the inconvenience.

8

In reply to Nandeesha:

You can change the clocking within a property. Below is an example. I am showing you the approach, you should be able to work out the details


// o_c_500k changes at negedge of the clock and 
// ADC_START goes low at the posedge of the clock.
property P; 
    int v; 
    @(posedge clk) (1, , v=n) ##0 $fell(ADC_START) |->        
       strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
              ##0 q_dynamic_delay(v) ##0 @(negedge clk) $changed(o_c_500k));
  // the q_dynamic_delay(v) is at the posedge clk  
endproperty 
  ap_P: assert property(P);  
  always @(negedge clk) 
  if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");

Ben SystemVerilog.us

9

In reply to ben@SystemVerilog.us:

Thanks Ben. It’s worked. You’re awesome. Will mark this as solution. Thanks for your advices and help.