Variable declared inside a static function

SystemVerilog
1

Hi, this is the code i tried to execute,


class base;
  static int i;
    static function  get();
     int a;
      a++;
      $display(a);
    endfunction
  endclass
module top;
  initial begin
    base b1,b2;
    b1.get();
    b1.get();
    b2.get();
  end
endmodule

the output was
1
1
1
why a is incrementing only once? and can we declare a non static variable inside a static function?
Can anyone please explain the operation of this code…
and if I declare the same function as

 static function static get()

i am getting the output
1
2
3

2

In reply to Manoj J:

‘a’ is an automatic variable that gets initialized to 0 on each call to get(). You can declare ‘a’ as a static variable if thst is what you want.

The syntax
static function static was made illegal in the 1800-2009 LRM to prevent the confusion you are having now.

See automatic variables inside static method | Verification Academy

3

In reply to dave_59:

Thanks dave!!