Variable bit select

SystemVerilog
,
1

I know that having a variable bit select range:


int a, c;
logic [15:0] b;

initial begin
  b[a:c];
end

is not allowed. Also I know that you can do part selects if the msb needs to be variable but the width is constant:


  b[a+:4]

but how can I achieve the reverse?


  b[15:c]

I need to take a variable remainder of a 64 bit signal that will be a different bit width each time…


  b[63:a]
2

In reply to ce_2015:

It would help if you showed some example values you are looking for. Maybe you just need a logical shift.

(b >> a)
3

In reply to dave_59:

So I am trying to take a non-evenly-divisible number of bits of a 64 bit signal that is in a queue. For example 20 bits. I want to take the first 20 bits of the 64 bit signal, then the next 20 bits, then the next 20 bits. When I get 60 bits processed, I need to take the final 4 bits AND 16 of the next 64-bit value in the queue to form my 20 bits, then continue on 20 bits at a time.


int current_msb;
int slice_width = 20;
logic [63:0] current_w, next_w;
logic [63:0] queue[$];
logic [slice_width-1:0] out_sig;
initial begin
   // looping mechanism
   if (current_msb >= slice_width-1) begin
      current_w    = queue.pop_front(); // queue filled by some other process
      out_sig      = current_w[current_msb -: slice_width];
      current_msb -= slice_width-1;
   end else begin // handle remainder
      int next_lsb = 63 - (slice_width-current_msb); // Get difference d [63:d]
      next_w       = queue.pop_front(); // guaranteed data present
      // Get remainder of current_w and beginning of next_w to fill all slice_width bits
      out_sig      = {current_w[current_msb:0], next_w[63:next_lsb]}; 
   end
end

Please let me know if I can clarify better

4

In reply to ce_2015:

Then you can shift both and bitwise OR them together instead of a concatenation.

out_sig = current_w << 63-current_msb | next_w >> next_lsb;