Hi folks,
Have been thinking about this for a while and thought I reached out to see if the wider community has any Best Known Methods for dealing with this kind of problem.
Consider this scenario, basic monitor, no clocking blocks or anything fancy, I would like to monitor for posedge of sigA, so in monitor code, we could have something like that:
class my_monitor extends uvm_monitor:
... // boiler plate code
task run_phase(uvm_phase phase);
super.run_phase(phase);
forever begin
@(posedge sigA) // do something
end
endtask
endclass
Now, this implementation (i.e: using @(posedge sigA) is suspectible to transitions from unknown states to 1. (i.e: X → 1 or Z → 1)
For example, consider such a sim:
- during time 0: sigA is X
- some initializer drives sigA to 1.
The above sequence of events will trigger the posedge in the monitor code at time0 which I would like to avoid.
Does anyone have any Best Known Methods in detecting a actual valid transition in your UVM monitors? (i.e: not from a unknown state)