Using wait statement before forking in forever loop resulting in a race condition

SystemVerilog
1

Hi,
In code below how can i avoid triggering of fork on negedge of enable.

  • Enable is phase synchronous to clock
  • Consider TH1 is finishing first than TH2

forever begin
  wait((enable) == 1'b1);  
    fork 
       begin:Th1
         @(negedge clk);
         @(posedge clk);
         //$display("Check passed ");
       end
       begin:Th2
         clk_period_int = clock_period;
         #(`TIMEOUT_FACTOR * clock_period_int);
         $display ("Error: Clock gated when enable is asserted at %t for instance: ABCDEF :: HIERARCHY :: %m ",$time);
       end
     join_any
     disable fork;
end //forever

Thanking in Advance

-Yash

2

In reply to ysaini:
Not exactly sure what you mean by “Enable is phase synchronous to clock” It might matter more how it is coded.

You might want to try

forever begin
  @(posedge clk iff enable);  
    fork 
       begin:Th1
         @(posedge clk); // negedge no longer needed
         //$display("Check passed ");
       end
...
3

In reply to dave_59:

The code i pasted is part of the checker to ensure that clock is available when enable is high.
Hence cannot use below statement.

@(posedge clk iff enable);

Not exactly sure what you mean by "Enable is phase synchronous to clock

I want to imply that posedge of enable and posedge of clk will be at same time-stamp.

Thanks
-Yash

4

In reply to ysaini:
I see this question is related to another question you recently asked. So far, the code you show makes no sense in relation to what you seem to want to check.

It might help to create a small testbench that generates stimulus for the signals you want to check, showing test cases for passing and failing checks. Then we can show you how to fix your code to do what you want it to do. (Oh, and I find it hard to believe you can’t get access to a reference clock)