Using variables in array range

SystemVerilog
1

Any time I try to use packed arrays in a for loop like,


        if (pwdata[127:96]) data_size = 4; //integer size
        else if (pwdata[95:64]) data_size = 3;
        else if (pwdata[63:32]) data_size = 2;
        else if (pwdata[31:0]) data_size = 1;


        for (int i=0; i < data_size; i++) begin
            write(paddr+i*4, pwdata[(i*32 + 31):i*32]);
        end

Gives the error

ERROR: [VRFC 10-2951] ‘i’ is not a constant
ERROR: [VRFC 10-1775] range must be bounded by constant expressions

How can I resolve this?

2

In reply to Husni Mahdi:

LRM section 7.4.6 Indexing and slicing of arrays states that the size of the part-select or slice shall be constant, but the position can be variable. You can use the ‘+:’ and ‘-:’ operators to specify the slice size:


if (pwdata[127:96]) data_size = 4; //integer size
else if (pwdata[95:64]) data_size = 3;
else if (pwdata[63:32]) data_size = 2;
else if (pwdata[31:0]) data_size = 1;
 
for (int i=0; i < data_size; i++) begin
  write(paddr+i*4, pwdata[(i*32 + 31) -: 32]);
end