Using $size in Parametrized Class

SystemVerilog
,
1

Hello everyone ,

I am facing issues while using $size in a parameterized class .

Here is the Sample Code ::



class A #(type T = int) ;

T a ;

bit [$size(a) - 1 : 0] b ;



endclass


A#() at ;
A#( .T(bit) ) ab ;

initial begin

at = new();
ab = new();
$display("Done");

end

Out of the 2 Simulators I tried it runs successfully on one while I get an Error on the other .

Is there a limitation of using $size in Classes ?

Thanks,
HV

2

In reply to himanshu valecha:

Using $size where a constant expression is required is not currently legal syntax due to a technicality in the LRM that has already been reported. Use $bits instead.

If your code works in an unparameterized class, or even outside a class, consider it a tool bug that needs to be reported to your tool vendor directly. (not here as this public forum is not for discussing tool specific issues)