Using $sdf_annotate inside a generate statement

SystemVerilog
1

We use a generate statement to instantiate multiple copies of our DUT in our testbench.

I am trying to add an $sdf_annotate task within the generate statement, to annotate a particular instance buried in the DUT.

So, question 1: is there anything wrong with this approach?

Assuming that the approach itself isn’t flawed, I’ll continue. The fourth argument to the $sdf_annotate system task is for a log file. Since there’s multiple copies of the thing I want to annotate, I’d like to have a log for each one. So I thought I’d use the genvar to create a string, but that’s not working for me.

Here’s the example code:


    generate
        for (genvar i = 0; i < NUM_DUTS; i++) begin : gen_duts
            dut_name dut_instance (.*)

            initial begin
                $sdf_annotate(...path to sdf file..., dut_instance.path.to.thing.i.want.to.annotate, , $sformat("sdf_%0d.log", i));
            end
        end : gen_duts
    endgenerate

The error I get is:

Error-[IAFSDFA] Illegal argument for $sdf_annotate task
...path to testbench source...
  Argument no. 4 must be a character string.
  Verilog task:
  $sdf_annotate("...path to sdf file...",
  dut_instance.path.to.thing.i.want.to.annotate, ,
  $sformat("sdf_%0d.log", 0));

So, question 2: how can I create a string within a generate statement that I can pass to the $sdf_annotate system task?

Any help is appreciated! Thanks in advance.