Using rand_mode( ) as a Constraint Guard

SystemVerilog
,
1

Hi ,

(1) LRM 18.8 says :: " Inactive variables ( Using rand_mode(0) ) are not randomized by the randomize() method, and their values are treated as state variables by the solver "

(2) In LRM 18.5.13 it says State Variable can be used as a Constraint Guard .

So I was trying to link the above 2 Cases in following Code ::



class A ;


rand bit [1:0] rv ; // Rand Variable 

rand bit [1:0] sv ; // Rand Variable which would act as State Varaible in Certain Cases


constraint CG {  
                   if ( sv.rand_mode() == 1 ) // [Q] Should/Will this work ?? 
                   {
                        sv < rv ;
		   }
              }		   


endclass 


A a1 ;


initial begin

a1 = new() ;

repeat(2)
begin

if ( a1.randomize() )
  begin
    $display("Success with %p",a1);
  end
end


end

Only 1 out of the 3 Simulators I tried this on Worked .

**[Q] Is it illegal to use rand_mode() as a Constraint Guard ?
**

Regards ,

AGIS

2

In reply to Etrx91:

The LRM say you cannot call rand_mode/constraint_mode to change the mode in a constraint, but does not prohibit using it as a state value in an expression.

I tried on 4 simulators and it worked on 2 of them, 1 said not yet implemented, and 1 gave an error. Note that the simulators on EDAPlayground are relatively very old.