Using %p after Upcasting

SystemVerilog
,
1

Hello everyone ,

I have a small code ::



module Main ;

class Base 

rand bit [1:0] a ;

endclass

class Ext extends Base ;

rand bit [1:0 ] b;

endclass

Ext  e ;
Base b ;

initial begin

e = new() ;

b = e ; // Up-Casting

if ( b.randomize() )  // randomize() is Virtual 
$display(" b is %p ",b);

end

endmodule

Should the Output Ideally have 2 Properties ( a && b ) OR Only 1 ( Only a ) ?? 

 I tried this on different Simulators and got 2 Different Results

Thanks in advance ,

Himanshu V

2

In reply to himanshu valecha:

The LRM defines %p for printing aggregate types as an assignment pattern. Classes are not considered aggregate types and does not define their use with assignment patterns. Some tools allow the use of %p with classes as a debugging aid, but the output is not defined. This is a tool specific issues and this forum is not for discussing those kinds of issues. Please contact your tool vendor.