Using ** operator for restricting for loop in SystemVerilog

SystemVerilog
1

I am trying to generate a parameterizable CSA tree. I am wondering if this for loop will work as intended:

generate
    for (x = 1; x < DATA_LEN_CLOG; x++) begin
        for (int j = 0; j < (DATA_LEN/(2**x))/2; j++) begin   <--- For loop in question
           :
           :
endgenerate

This for loop is used to reduce each iteration to powers of 2. Will these properly restrict the for loop in synthesis?

2

In reply to blaze09:

If these are both generate-for loops (i.e.
for (genvar x;…) for (genvar j)), then it doesn’t matter what operators you use as long as x and j evaluate to unique integers.

Assuming DATA_LEN_CLOG = $clog2(DATA_LEN), Then what you have should work, but you never stated what your intentions are.