Using modports to restrict access to interface signals

SystemVerilog
, ,
1

I have a question that I seem to be having a hard time finding the answer for in the standard. If I define a modport that specifies a subset of the signals in the interface, does that mean that if I use it to connect modules, then only that subset should physically exist at that connection? What if I try to access a signal from a modport instance where that signal is not part of its subset?

TIA

2

That is the whole point of a modport - they define a subset signals that become ports of the module. The signals that are not part of the modport do not get connected and thus you have no access to them. Once defined, odports are only referenced in the port connection.

interface my_intf;
  wire a;
  wire b;
  wire c;
modport sub1(input a, output c);
endinterface
module my_mod(my_intf.sub1 p); // this is effectively replaced with input p.a, output p.c
  always @(p.a)
    p.c <= p.b; // this will be a compilation error - no access to p.b
endmodule
module top;

 my_intf i1();
 my_mod m1(i1.sub1); // this is effectively replaced with i1.a, i1.c

endmodule