Using macros as util functions

SystemVerilog
1

Hi,
Can I define my util methods as macros and reuse them in my code wherever I want.
Ex: I define addition, multiply, division as macros and would like to use in my code.
define add(in1,in2,sum)\

My code

add(a,b,c)

Any issues in this approach or any better approach.

Thanks

2

In reply to nalsai:

It would help to explain a bit more context. Why not use a function or a module? Where is the code going to be located?

3

In reply to dave_59:
Thanks for the reply.

To Simplify the code and convert modules to macros for emulation.
I would like to know if any limitations to use macros

No restriction of using functions or modules but I am trying if I can use macro.

Thanks.

4

In reply to nalsai:

A macro is just a text replacement feature; it knows almost nothing about SystemVerilog syntax.

5

So, if I write some functions/modules to be reused by the team, any approach to hide them and just give user the function/instance signature so that they can use in their code as built in utilities.