Using macros in signal name

SystemVerilog
,
1

I’m using macros in a signal name. But ,I see compilation errors

define PATH rx define REPLACE(x) x

class my_class;

int v_PATH ; // 1st approach int y_REPLACE(`PATH) ;//2nd approach

endclass

Both the approaches are giving me error. What is the correct way of doing it. I want to declare two variables
int v_rx;
int y_rx;
But the suffix should come from a macro

2

In reply to kartavya:
You can only join characters of an identifier inside the body of a macro. What you want is

`define PATH rx
`define JOIN(x,y) x``y

class my_class;

int `JOIN(v_,`PATH) ; // 1st approach
int `JOIN(y_,`PATH) ; //2nd approach

endclass