`define SOME_MACRO 2
`define SOMER_MACRO 0
`define OTHER_MACRO 3:0
bit [`SOME_MACRO:0] a;
bit [`SOME_MACRO:`SOMER_MACRO] b;
bit [`OTHER_MACRO] c;
which of these work? and why?
i have used the declaration of a
in my code, which was a signal of a module, and apparently verdi when selecting the signal recognizes the width as [0:0] instead of [2:0] though i am not sure whether that is a bug in verdi or how the compiler actually understands the line, considering `SOME_MACRO is 2 and not 0.
thanks and best regards