Using genvar in hierarchical path in generate but not for array index

SystemVerilog
1

I’m pretty sure the answer to the following is what I want to do is not possible in Sysverilog. If someone knows different or can confirm my suspicions please respond.

I’m always having to deal with hookup to rtl that has instance names like foo_0, foo_1. I can’t get the rtl recoded to use an array of instances so normal hookup code in testbench would require something like this:

assign some_interface.somvar = foo_0.somvar,
etc…
Tedious as you have to have one statement per “foo” instance. If the foo instances were an array you could just use generate. I tried to play with a macro as shown in the example below but this fails too since the macro expansion occurs before the generate statement so it gets “foo_insti” instead of “foo_inst0, foo_inst1, etc…” using the genvar variable value.

Example code:

`define foo(i) foo_inst``i``

module foo ();
   logic go;
   int   idx;
   
   always@(go)
     $display("%t:I'm in foo_%0d",$time,idx);
endmodule // foo

      
module testbench;

   reg clk;
   reg reset_n;

   
   foo foo_inst0();
   foo foo_inst1();

     // Works:
//   assign foo_inst0.idx = 0;
//   assign foo_inst1.idx = 1;
   
// Does not work:
   generate
      genvar i;
      for (i=0;i<2;i++)
        assign foo.idx = i;
   endgenerate
 
   
   initial begin
      clk = 0;
      reset_n = 0;
      #10;
      `foo(0).go = 1;
      #10;
      `foo(1).go = 1;
      #10;
   end
endmodule // testbench
2

In reply to russ.petersen@broadcom.com:
Hi Petersen

As per per above code what I understand is,you are trying to assign one variable inside module instance which is generated with help generate block.I Have modified your code to achieve your requirement.In place of using assignment statement,I have declared input variable and assigned value to module input variable through instance creation.I believe this logic helps your requirement.

module foo (input int idx);
   logic go;
 
   always@(go)
     $display("%t:I'm in foo_%0d",$time,idx);
endmodule // foo
 
module testbench;
   reg clk;
   reg reset_n;
   generate
      genvar i;
      for (i=0;i<2;i++) foo foo_inst[i:i](.idx(i));
   endgenerate

  initial begin
     clk = 0;
     reset_n = 0;
     #10;
     foo_inst[0].go = 1;
     #10;
     foo_inst[1].go = 1;
     #10;
  end
endmodule // testbench