Using $display in consequent in System Verilog assertions

[sudhirbarefoot2018]

I have a simple assertion to check clock period. The assertion fails when I add $display() in consequent. If I remove remove $display in consequent, it passes. I have used $display() in antecedents before. Can we use $display() in consequent?. Below is the code.

property clk_period ( real exp_clk_period );
time current_time;
disable iff (count>10)
(en, current_time = $time) |=> ((clk_period == ($time - current_time)), $display(“dfiff=7.2%f”, $time - current_time));//FAILS

//(en, current_time = $time) |=> ((clk_period == ($time - current_time));//PASS

endproperty : p_period

chk_clk_period: assert property(@ (posedge clk)
clk_period(exp_clk_period))

[ben2]

In reply to sudhirbarefoot2018:
Rather than debugging your code, here is code that works as expected.

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;    
	bit clk, en=1'b1, b;  
    initial forever #10 clk=!clk;  
    realtime exp_clk_period=20;
    initial begin
        $timeformat(-9, 1, "ns", 8);
        $display("%t", $realtime);
    end 
    property p_period ( realtime exp_clk_period );
        realtime current_time; 
        // disable iff (count>10)
        (en, current_time = $realtime) |=>
        (exp_clk_period == $realtime - current_time, 
        $display("dfiff=%t", $realtime - current_time));// OK      
        //(en, current_time = $time) |=> ((clk_period == ($time - current_time));//PASS
    endproperty : p_period
    
    ap_period: assert property(@ (posedge clk)   p_period(exp_clk_period)); 
endmodule  
// sim  results 

#    0.0ns
# dfiff=  20.0ns
# dfiff=  20.0ns
# dfiff=  20.0ns
# dfiff=  20.0ns
 

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