Using constraint set

SystemVerilog
,
1

Hi, I am running the following code to randomize the size and contents of an array based on different values of a,c,d

class predicate;
rand bit a,c;
rand int d;
rand int e;

constraint c1{//solve a before c,d;solve c before d;
d inside {0,1,2,3};
a == 0 → c == 0 → d == 0 → {e.size == 5; foreach (e[i]) e[i] inside{[1:5]};}
a == 0 → c == 1 → d == 1 → {e.size == 10; foreach (e[i]) e[i] inside{[6:10]};}
a == 1 → c == 0 → d == 2 → {e.size == 15; foreach (e[i]) e[i] inside{[11:15]};}
a == 1 → c == 1 → d == 3 → {e.size == 20; foreach (e[i]) e[i] inside{[15:20]};}
}
endclass

When randomizing the object of this class I am getting warning about the size of the array as:

    Variable e.size() has value > 10000, which may cause severe performance degradation.
    Please try to reduce the array size.

Please help me understand the issue here.

Thank you

2

In reply to Naveenkb:

Chaining implication operators does not work the way you think it does. Two things to remember are

  • Implication is a Boolean operator: {a → c} is equivalent to {!a || c}

  • Associatively is right to left: {a → c → d} is equivalent to {a → {c → d}}

    So your constraint (ignoring the foreach)

a == 0 -> c == 0 -> d == 0 -> {e.size == 5}

is equivalent to

a != 0 || c != 0 || d != 0 || e.size == 5

So a=0, c=0, d=1 becomes a valid solution, then the size of e is unconstrained.

I think your intent is

a == 0 && c == 0 -> {d == 0; e.size == 5; foreach (e[i]) e[i] inside{[1:5]};}
a == 0 && c == 1 -> {d == 1; e.size == 10; foreach (e[i]) e[i] inside{[6:10]};}
a == 1 && c == 0 -> {d == 2; e.size == 15; foreach (e[i]) e[i] inside{[11:15]};}
a == 1 && c == 1 -> {d == 3; e.size == 20; foreach (e[i]) e[i] inside{[15:20]};}
3

In reply to dave_59:

Understood how it works. Thank you very much Dave.