Using Cast operator inside an Always block

SystemVerilog
,
1

I am trying to get rid of pesky Arithmetic operation is self-determined context linting issues by using the casting operator in SystemVerilog.

Sample Code:


logic [7:0] a;
logic [3:0] b;
logic [3:0] c;

always @(posedge i_clk) begin
   if (i_rst) begin
    c <= '0;
   end else if (8'(b+1'b1) < a) begin
    c <= c+1;
   end
end

I am expecting this to get rid of the warning that (b + 1’b1) Arith Op is self-determined. but it does not. I have to put that into a separate continuous assignment statement to git rid of the issue. Is there a way to avoid that?

2

In reply to zmax:

This looks like a misunderstanding by your linting tool. The result of a static cast is self-determined, but not the expression inside it.