Using Case Equality / Inequality within property / sequence

SystemVerilog
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1

Hi All ,
I was curious to know whether case equality ( === ) , case inequality ( !== ) are legal within property / sequence
So I tried a scenario as an alternative to $isunknown : edalink

Using +define+ALT1 the output is as per expectation however when using inside operator via +define+ALT2 ,
why does the assertion fail at time : 45 ?

When a is 2’b00 , my expectation is that inside operator would return 0 and via !0 the assertion would pass

How does the inside operator function with 4-state values ?

2

In reply to Have_A_Doubt:

The inside set-membership operator uses wildcard equality, not case equality. That means an X or Z on the RHS gets treated as a don’t care, so its result will always be true in this example. The property
prop negates that result, so the assertion always fails.