I am new to system verilog.
I was writing a test bench to test my SPI master code . I came across something called as BFM provided by SysWip(http://syswip.com/)
It gives, master and slave Verification IP folders. The folders have an interface and a package file.
I have a question here, to test my master code, i will have to make use of only the slave verification IP..am i right?
also how is the connection made to the interface? How do i instantiate the interfce and in which file the connections are done.
Below is a part of my master.sv amd master_tb.sv code.
output [SLAVES-1:0] slave_select
//code to shift in and out data
wire [2:0] slave_select;
//part of my testbench code i have typed here.
My question is,
- where do i import the interface, in which file?
- do i need both the interfaces-master and slave?
- how do i do the connections?
- How do i do the data transfer?