Using 4-state as Constraint Guard

SystemVerilog
,
1

Hi all ,


LRM 18.3 says :: " Constraints support only 2-state values. The 4-state values (X or Z) or 4-state operators (e.g., ===,
!== ) are illegal and shall result in an error. "

Is this applicable to constraint Guards too ?



logic [1:0] a ;
rand bit [1:0] b ;

constraint VAL {  if ( a == 0 ) 
                    { b == 0 ; }
		   else
                    { b == 3 ; }
               }

If I fail to initialize a before calling randomize() [ Remains at default 4-state X ] what should the result be ?
Should it go ahead with randomization OR take the else part of the Constraint Guard ?

I observe both results on different simulators ( I understand this forum isn’t meant to discuss simulator issues ) .
Some give Error and while some give a warning and give b as 3

Thanks

2

In reply to Have_A_Doubt:

The LRM is not very clear on the expressions allowed in constraint guards. You can bypass all this by putting the expression inside a function.

function bit guard ();
  return a === 0 ;
endfunction // guard
 
constraint VAL {  if (guard() ) 
                    { b == 0 ; }
		   else
		    { b == 3 ; } 
               }