Use of wait statement

SystemVerilog
,
1

I have to write a verilog code that displays few signals as the output. I have to display a few reads and writes. The value of Read data during a read transaction changes sometime after the negative edge of the clock and before the positive edge of the next clock. I want to display the read data. How can i display the read data. I tried the following code :

@(negedge clk)
wait(rdata)
$display(rdata)

But there might be consecutive non-zero read transactions. So, I am stuck here :

@(negedge clk)
//wait for rdata to change
$fdisplay(rdata)

As I am new to verilog and SystemVerilog, I can not figure out how to wait until the data changes. Please help.

Thank you

2

In reply to nimesh13:

@rdata means wait for the rdata to change. But why not display it on the @(posedge clk)?

3


In reply to dave_59:

The thing is that if I read at one clock cycle, the other clock cycle might represent a write transaction. If I show it with a @(posedge clk) then I would displaying a wrong transaction at a wrong time. Hence not showing it with @(posedge clk)

Also attaching a picture to give an idea about the scenario. The rdata is not 1 bit, it is 32-bit. Shown here for simplicity

Although I thought of a solution, but it is not giving the correct output.


@(posedge clk)
begin
$fdisplay(wdata);
$fwrite(file,wdata);
end
@negedge(clk)
begin
wait(clk==1);
$fdislplay(rdata);
$fwrite(rdata);
end

Help me rectify this. Thank you.

4 
forever begin
  display();
end

task display();
  fork:p1
    begin
        @negedge clk;
        @data;
        $display("%d",data);
    end
    begin
        @(posedge clk);
    end
  join_any
  disable p1;
endtask

tell me if there is any corrections.

5

In reply to juhi_p:

Can you please tell why you have used fork in your code?