Use regular expression in systemverilog to remove "anything start with some predefined letter "

SystemVerilog
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1

Hi everyone,
i have one queue of string, i want to remove "anything which start with UVM ". for example UVM_VERBOSITY,UVM_TESTNAME etc.
i know how to do it using perl because it supports regular expression very well. but in Systemverilog regex does not support that much (at least in vcs, ignore it).

module tb;
  initial begin
    string test_queue[$]={"xyz","abc","UVM_VERBOSITY","UVM_TESTNAMES","systemverilog"};
    $display(" Q : %p",test_queue);
  end
endmodule

Output : 
Q : '{"xyz", "abc", "UVM_VERBOSITY", "UVM_TESTNAMES", "systemverilog"}

 i want Q : '{"xyz", "abc", "systemverilog"}

can you help me how to procced , to remove them.

Thanks,
Alok

2

In reply to Alok_Mandal:

You don’t need regular expressions for simple matches like this

module tb;
  string test_queue[$]={"xyz","abc","UVM_VERBOSITY","UVM_TESTNAMES","systemverilog"};

  initial begin
    test_queue = test_queue.find(s) with ("UVM" != s.substr(0,2));
    $display(" Q : %p",test_queue);
  end
endmodule

If you really need regular expressions, the UVM provides uvm_re_match(re,str).