Use a package structure compiled in library A from library B

SystemVerilog
1

Hi,
Coming from VHDL world i’m used to compile parts of the design in seperate libraries, i.e. module A in library A, module B in library B.

I’m trying to do the same in system verilog without much success when i try to use a structure for my module IOs.

Code example:
module1.sv:

package my_types_pkg;
typedef struct
{
logic read;
logic write;
} record_test_t;
endpackage
module module_1(
my_types_pkg::record_test_t t_tb
);
endmodule

module1_tb.sv:

module top;
my_types_pkg::record_test_t t_tb_1_s;
module_1 module_1_1(
.t_tb(t_tb_1_s)
);
endmodule

When i compile both files in the same library i have no issue:
vlib work
vlog -sv -work work module1.sv
vlog -sv -work work module1_tb.sv

However when i try to compile them in different libraries it tells me the structure i’ve defined is undefined… :(
vlib work
vlib module1
vlib module1_tb
vlog -sv -work module1 module1.sv
vlog -sv -work module1_tb module1_tb.sv

==>
vlog -libmap_verbose -sv -work module1_tb module1_tb.sv
QuestaSim vlog 10.2c_5 Compiler 2013.11 Nov 19 2013
– Compiling module top
** Error: module1_tb.sv(41): (vlog-2164) Class or package ‘my_types_pkg’ not found.
** Error: module1_tb.sv(41): near “::”: syntax error, unexpected ::, expecting IDENTIFIER or TYPE_IDENTIFIER

I’m not sure how to tell system verilog to look in another library for this package.
In VHDL it would be something as simple as:
library module1;
use module1.all;

Thanks.
Nicolas.

2

Hi Nicolas,

A systemverilog treats package in a different manner.
Here, you need to import the package and then you can take a variable of structure “record_test_t” type. Please find the modified code below.

package my_types_pkg;
   typedef struct 
   {
      logic read;
      logic write;
   } record_test_t;
endpackage
module module_1(
                input t_tb
                 //my_types_pkg::record_test_t t_tb
               );
  import my_types_pkg::record_test_t;
  record_test_t  t_tb;
endmodule


module top;
  import my_types_pkg::record_test_t;
  record_test_t  t_tb_1_s;
  module_1 module_1_1(
                      .t_tb(t_tb_1_s)
                     );
endmodule

You can play with this code at typedef struct in package - EDA Playground

3

The problem is that work libraries in Verilog/SystemVerilog are not defined unless you use a configuration. But this simple solution is just to add -L module1 to the command line.

BTW, you should not be using -sv on the command line as all files with the *.sv are already recognized as being SystemVerilog source. If you ever use any older Verilog source code, you want to keep them interpreted as Verilog. Otherwise any SystemVerilog keywords used as identifiers will cause a compiler error in those files.

4

In reply to dave_59:

Indeed i found out in the meantime the same solution, adding -L module1 solves the issue. Thanks a lot!

5

In reply to bdreku:

actually the code as i wrote is functional. So i do not quite understand why i would need to modify it as you shown. I will however keep it in mind. Thanks.