Use of number in instance_name

SystemVerilog
,
1

Hi,

I have got stuck in one point in which I need to use numbers in instance_name like,

no_of_ports_0
no_of_ports_1
no_of_ports_2
…
…
no_of_ports_n

‘n’ can be any Parameterised number.

How can I do it?

I have once done it using ‘generate’ block, but not getting syntax now.

–
Regards,
Harshit

2

In reply to electron:

Can you show what one instance would look like?

3

In reply to dave_59:

Hi dave_59,

Thanks for replying.

Suppose I have interface module is below,

interface my_if;

now if n is 2 then i would like to generate following kind of thing,

my_if no_of_lane0 [0:6]
my_if no_of_lane1 [0:6]
my_if no_of_lane2 [0:6]

here array size of each lane should be fixed as 7, And I would like generate n numbers of these array as shown above.

I tried as no_of_lane [0][0:6], but two dimensional instance creation for interface module is not possible that it shown in error.

I don’t want to create no_of_lane [0:6 * n] kind of thing as it would not fill my expectations.

4

You would need to use a generate/for-loop as you have found that arrays of instances only support a single dimension.

genvar i;
for(i=0;i<N;i++) begin : lane
 my_if i[0:6]();
end

Then you can reference

lane[0].i[0]
lane[0].i[1]

5

In reply to dave_59:

Thanks dave_59 its work and new for me.

But here when I will use that created instance, Feeling like use a hierarchy kind of thing lane[1].i[3]

Is there any way to use simple lane_1[3] or lane_0[2] something like?


interface my_if();
endinterface : my_if

module top();
  my_if lane_0 [0:6];
  my_if lane_1 [0:6];
  my_if lane_2 [0:6];
endmodule : top

I would like to create this lane_0 to lane_n as per defined parameter.

6

In reply to electron:

There is no way to program the characters that make up an identifier in a loop using SystemVerilog. Some people have tried using an external text pre-processor. But then you have deal with two sets of sources.

Is there a reason you can’t use the generate syntax?

7

In reply to dave_59:

Ok, I expected this.

And the reason for finding alternate solution is, generate block makes increase the variable name as you described above lane[0].xyz[0] with prefix generate block name.

I am completing this thread here.

Thanks a lot dave_59

8

In reply to electron:

Hi,

I proceed with above solution but at one place I got the Cross-module reference error.
Ex. Code:


interface my_if();
endinterface : my_if
//-------------------------------------------
class A;
  function new(virtual my_if intr[0:1]);
  endfunction
endclass : A
//-------------------------------------------
module top();
  generate
    for(genvar i = 0; i<2; i++) begin : IF
      my_if inter[0:1]();
    end
  endgenerate

  main main_i();
endmodule : top
//-------------------------------------------
program main();
  A a[0:2];
  initial begin
    for(int j=0; j<2; j++) begin
      a[j] = new($root.top.IF[j].inter);
    end
  end
endprogram : main

Here in program block IF[j] creating a problem, it is demanding fixed value like IF[0] etc. But I need to construct class A’s instance according to the interface instances.

Could you please give your inputs.

9

In reply to electron:

You cannot reference the index of an array of instances or generate loop create instance with a variable. You must use a constant or another generate loop to access it. So instead of your initial/for loop, change it to a generate-for/initial.

module main();
  A a[0:2];
generate
  for(int j=0; j<2; j++) begin : init_itf
    initial
       a[j] = new($root.top.IF[j].inter);
    end : init_itf
endgenerate
endmodule : main
10

In reply to dave_59:

Great, Thanks a lot dave.