Use of Nested class in System Verilog

can anyone tell me where we use nested class or what is practical use of nested class?

The SystemVerilog LRM says:

Like modules, classes are scopes and can nest. Nesting allows hiding of local names and local allocation of resources. This is often desirable when a new type is needed as part of the implementation of a class. Declaring types within a class helps prevent name collisions and the cluttering of the outer scope with symbols that are used only by that class.

If there is a Class B that is tightly-coupled to, and will only ever be instantiated by, Class A, it makes sense for Class B to live inside Class A. This prevents other entities from instantiating Class B when they’re not supposed to.

In reply to sbellock:

The most practical use of this features is when using macros that declares class B for use by specific class A. Then you have another class C that has the same macro declaring class B.

Look at the example here that has the macro outside the class. But if there were multiple cases of this, nesting the macro would avoid name collisions.