Use loop index value in hierarchy path connections

SystemVerilog
1

Hi,

I have 2 instances of req_agent in top_env.
I want to connect the monitor port of req_agent to predictor class like this:

req_agent[0].monitor.rd_cpl_data_out_port.connect(predictor_model.req_agent_rd_cpl_0);      
req_agent[1].monitor.rd_cpl_data_out_port.connect(predictor_model.req_agent_rd_cpl_1);

I want to use foreach loop for this like:

 foreach (req_agent[index]) begin
       req_agent[index].monitor.rd_cpl_data_out_port.connect(predictor_model.$sformatf("req_agent_rd_cpl_%d",index));   
  end

I am getting error for $formatf:
Error-[ICTTFC] Incompatible complex type usage

Any other way to do this?

Thanks

2

In reply to vineet_sharma:

You can’t create instance references from strings. You will need to do this manually.

3

In reply to vineet_sharma:

See How do I iterate through hdl hierarchy with foreach/generate loop | Verification Academy

4

In reply to vineet_sharma:

Declaring req_agent_rd_cpl as an array in predictor model would help.

Example,
// in predictor_model

// in predictor_model
req_agent_rd_cpl[2];


// iterate through foreach loop
foreach (req_agent[index]) begin 
req_agent[index].monitor.rd_cpl_data_out_port.connect(predictor_model.req_agent_rd_cpl[index]);   
end

With the hard coded declaration neither foreach or any other loop will work.