Usage of task parameter

SystemVerilog
1

Dear All,

I’ve been trying to understand the usage of task parameter
Here is one example,

  task send_to_dut(input bit [5:0]  length,
                                        bit [1:0]  addr,
                                 output bit [7:0]  parity,
                                        int packet_delay);

If I declared as above, length and addr are assigned as input ? and parity and packet_delay are assigned as output ?

2

In reply to UVM_LOVE:

Yes, correct