Usage of task in assertion

SystemVerilog
1

I have run the below code using VCS simulator and I’m getting the error saying
“Error-[SVA-POISC] Property operator in sequence context
testbench.sv, 38
tb, “(a |-> ( 1, initial_task ))”
Property operator usage is not allowed in sequence context. Implication used
in sequence context.”

Please let me know what may be reason.

Code:


module tb();
  bit clock;
  time initial_time;
  time next_time;
  
  bit a;
  
  initial
    begin
      a=1;
      #31;
      a=0;
    end
  
  always #10 clock=~clock;
  
  task initial_task();
    initial_time=$time;
  endtask
  
  task next_task();
    next_time=$time;
  endtask
  
  property prop1;
    @(posedge clock) a |-> (1, initial_task());
  endproperty
  
  property prop2;
    @(posedge clock) a |-> (1, next_task());
  endproperty
  
  property p;
    prop1 ##1 prop2;
  endproperty
    
      assert property (p);
   
endmodule
2

In reply to Pavan Acharya G:

That’s not a very helpful error message; other tools point out that you cannot do

prop1 ##1 prop2;
3

In reply to dave_59:

Thank You Dave. Got to know where is the issue.