Usage of RHS delay(intra-assignment delay) in non-blocking assignment in a procedural statement

SystemVerilog
, ,
1

I have a GLS simulation, which makes use of a netlist.

One of the modules makes use of an intra-assignment delay which is defined in a define. When the same code is run in RTL environment there is no compilation error, but for a GLS run there is a syntax error for the data_sync_int <= **#seq_unit_delay** data;

I replaced the seq_unit_delay with a number(1, in this case, or any other number if define is removed) then it compiled successfully.
Is it bad coding technique to use `define in the intra-assignment delay in GLS simulation?

The code goes like this.

`define seq_unit_delay 1

module trc_tech_syncff #(parameter DATA_WIDTH = 16) (
input clk,
input [(DATA_WIDTH-1):0] data,
output reg [(DATA_WIDTH-1):0] data_sync
);

reg    [(DATA_WIDTH-1):0] data_sync_int;

always @( posedge clk )
begin
  data_sync_int <= **#`seq_unit_delay** data;
  data_sync     <= **#`seq_unit_delay** data_sync_int;
end

endmodule

2

In reply to Curious_cat:

Verilog does not know the difference between RTL and GLS simulation—it’s only a difference in which constructs you use more.

It would help to see the exact error message you are getting.

3

Is it possible the precompiler is inserting a space? Did you try putting the “#” in the 'define?

4

In reply to dave_59:

The exact error message is
Error-[SE] Syntax error
Following verilog source has syntax error :
“/nfs/site/stod/ZZC_20.2/tcp-zzc/containers/trcc_con/subIP/TRCC/trc_tech/trc_tech.vh”,
146: token is ‘;’
data_sync_int <= #`seq_unit_delay data;

5

[i]In reply to Wes:[/i

Space does not matter.
# is used for the intra-assignment delay and cannot be put in the `define

6

In reply to Curious_cat:

Is your define statement for seq_unit_delay exactly as you wrote above, or are there conditional statements like `ifdef around it?

7

In reply to dave_59:

ifdef is missing for this particular module.
Other modules have a ifdef in them.

Ex:
_ifdef DC_ ec0fkn200ab1d02x5 dff00( .d1(d1), .d2(d2), .clk(clk), .o1(o1), .o2(o2) ); else
always @ (posedge clk) begin
o1 <= #seq_unit_delay d1; o2 <= #seq_unit_delay d2;
end
`endif
endmodule