Usage of 4 state & 2 state data type

  1. why it is recommended to use 4 state data type for synthesizeable RTL code ?
  2. In a testbench, why is is recommended to use 2 state data type to drive stimulus into DUT & 4 state to capture the design output ?

In reply to shekher201778:

  1. why it is recommended to use 4 state data type for synthesizable RTL code ?

In simulation and in tool analysis to verify the effects of the X propagation.
Uninitialized registers may cause issues in the design.

  1. In a testbench, why is is recommended to use 2 state data type to drive stimulus into DUT & 4 state to capture the design output ?

You can use type "logic"in the drivers as they are typically assigned a value before being driven.
Capturing the Xs in the outputs is important because it may signify an issue with the design, such as bad initialization or maybe data collision.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: * Component Design by Example https://rb.gy/9tcbhl
  1. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/