task start();
pkt = new;
//initial
repeat(20)
begin
@(posedge in_intf.clk);
if(out_intf.cb_out.full!=1)
begin
in_intf.cb_in.we <= 1'b1 ;
in_intf.cb_in.re <= 1'b0 ;
in_intf.cb_in.rst <= 1'b0 ;
in_intf.cb_in.data_in <= pkt.count;
drv2sb.put(pkt.count);
$display($time," Driver : data being given to DUT ",pkt.count);
$display($time," Driver : write enable high given to DUT ");
pkt.count <= pkt.count + 1;
end
else
begin
$display($time," Driver : FIFO is full %b, providing read enable ",out_intf.cb_out.full );
in_intf.cb_in.re <= 1'b1 ;
in_intf.cb_in.we <= 1'b0 ;
end
end
endtask
In the above code, initially when FIFO was not full, testbench was providing data in the reactive region and it was getting updated in active region of same time slot in Design. When design(DUT) gave the output as FIFO full, it was sampled by Driver and it gave read enable(re) as high.So, now this re was given high in the reactive region of the time slot which was the next posedge of FIFO full. As per my Understanding, if read enable was given high in reactive region it should get sampled by design in the active region of same time slot and appropriately DUT should have removed a data from FIFO. So, now on next clock edge While driving from testbench it should see that fifo is not Full now and hence can be given one data to write. But opposite to this what i observe is again Read Enable is driven by TB, because its not able to sample that one data has been moved out of design. Can someone help me out here ?