Updating checkers for GLS

SystemVerilog
,
1

Most of our whitebox checkers are developed at the time of RTL verification. Re using these checkers during GLS is tedious, as we have to manually update hierarchical path of the signals used in the checker.

Is there a way to make this process easier?

2

In reply to absingh:

If synthesis is flattening the hierarchy you are out of luck unless it provides some mapping file for you.