In reply to S.P.Rajkumar.V:
2) The assertion that I am working on is not so simple. So, I'd not want to jump into tasks at this point. I made the assertion looked very simple, so that the experts here can concentrate on my requirement instead of getting puzzled with the assertion details.
For complex assertions I would use the task method as described in my referenced paper; my choice. Keep in mind that the task method ( https://goo.gl/FGJhKD
) behaves and is fired in a manner similar to SVA, but with more flexibility. Don't get me wrong, I like SVA (I wrote several books and papers on the subject)
, but there are instances when SVA is just not powerful enough, and one needs to resort to raw SystemVerilog, but with the firing approach of SVA; by that I mean every threat (and local variables) of an assertion is independent of other threads. That is why the tasks are automatic
, and every task is fired with a fork/join_none
. This additional comment is for the general audience, you most likely know that.
3) For now, I will proceed with "##1 $fell(a) |-> (a==1'b1);" (by modifying the consequent too accordingly) unless someone else suggests another better solution.
I am wondering what you mean by (by modifying the consequent too accordingly)
If you worry about the ##1 in the antecedent, you shouldn't. Except for the first cycle,
@(posedge clk) ##1 $fell(a) |-> (a==1'b1);
// is SAME AS
@(posedge clk) $fell(a) |-> (a==1'b1);
// consequent starts at the fell(a). The only difference between the two is that
// the first endpoint occurs on the 2nd clock, Thereafter, an endpoint occurs at every clock,
// just like the case of @(posedge clk) $fell(a) |->
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