Unique values without randc / unique Constraint

SystemVerilog
,
1

Hi all ,

Is there a way to achieve a unique random number without using randc ( Size is Simulator dependent ) OR unique Constraint ?

Here is what I could think of


  class A ;
  rand int unsigned i ;
       int unsigned i_q[$] ;

  constraint UNIQUE_VALUES { !( i inside { i_q } ) ; } 

 // In post_randomize() function  
    i_q.push_back( i ) ;

Now this has performance limitation if data type is changed to long int ( as size of Queue would be too large )

I could also use ::


class A ;
  rand int unsigned i ;
       int unsigned cntr ;

  constraint UNIQUE_VALUES { i == cntr  ; }
// In post_randomize() function  
    cntr++ ;

Is there a better way ?

2

In reply to TC_2017:

If you’re looking for better performance, it would help to explain why you don’t want to use randc or unique constraints. If you simply need unique IDs that don’t have to be random numbers then you can use your second code, or more simply:

class A ;
  rand int unsigned i ; 
  constraint UNIQUE_VALUES { i == const'(i) + 1  ; }
3

In reply to dave_59:

I remember reading that randc has limitation on max size it can support .( Simulator dependency ) .

In one of my current reviews on SystemVerilog I was asked this question .
There was restriction on using unique constraint from my mentor so …

I do think that an alternate possibility could be using a logic based on unique number algorithm ( which doesn’t make sense practically since these are what simulator tools are for )