Uniqe assertion label name

SystemVerilog
,
1

Hi,

I want to control our channel timing during data transfer with assertion and also i create a assertion with genvar up to channel number.


proerty ch_timing(param1,param2,param3);
   @(posedge clk)
   .... condition.....
endpropery

generate
for(genvar i = 0; i<ch_number; i++) begin: gen_label_name
   label_name: assert_property(ch_timing(...));
   end
endgenerate

in the above code, when i look at the assertion, assertion seems to be “…/gen_label_name[0/1/2]/label_name”.
i want to see label_name such as gen_label_name[0/1/2**].

Thanks

2

In reply to asvn:

That’s not possible, but you can get close to it by using:


for (genvar i = 0; i < ch_number; i++) begin: assertions
  assert_name: assert_property(ch_timing(...));
end

This will give you assertions[0].assert_name, assertions[1].assert_name, etc.

3

In reply to asvn:

That’s a tool dependent thing. gen_blok[i].asssertion_label // i==1, 2, 3, …
Ben

4

In reply to Tudor Timi:

when i try to add this assertion to test plan, each of them seems to be same, how can i identify which one channel_1.
In your example i reach this string “assert__asert_name” for all assertion.

5

In reply to ben@SystemVerilog.us:

In reply to asvn:
That’s a tool dependent thing. gen_blok[i].asssertion_label // i==1, 2, 3, …
Ben

Is there are any solution to identify which one is channel_1, because when i try to add assertions to test plan, i only reach same assertion name for all assertions.

6

In reply to asvn:
With the tool I am using I see the path.assertion_label For example,
/top/genblk[0]/my_assertion_label
/top/genblk[1]/my_assertion_label

/top/genblk[7]/my_assertion_label
Why can’t your testplan use the [i] and make more generic; after all, it’s English
Ben

7

In reply to ben@SystemVerilog.us:

Yes, you are right. I talked with tool designer i am using, and also it has a switch that open the each path step by step.

Thank you for your help.