Uniform Contribution from constraint

Dear All,
I’m trying to understand uniform contibution from constraints in systemveriog.
I made the example as the below,

// Code your testbench here
// or browse Examples
class A;
 rand bit [7:0] pattern;
 rand bit mode;
 constraint c{
   solve mode before pattern;
   mode dist {1:=10, 0:=10 };
     mode -> pattern == 8'b10110110;
   }
endclass


module test();
initial begin
  for (int i =0; i< 10; i++) begin
  A a =new();
  a.randomize();
    $display("mode: %h, pattern: %b", a.mode, a.pattern);
  end
  
end
endmodule

and I got the result as below

mode: 1, pattern: 10110110
mode: 0, pattern: 00110011
mode: 1, pattern: 10110110
mode: 1, pattern: 10110110
mode: 1, pattern: 10110110
mode: 1, pattern: 10110110
mode: 1, pattern: 10110110
mode: 1, pattern: 10110110
mode: 0, pattern: 01011011
mode: 0, pattern: 01001111

My expectation was that the probability of mode 0 and 1 is 50% and 50%. because “solve mode before pattern”.
But 3 of mode 0, 7 of mode 1, I have not 5 mode 0, 5.
Did I make wrong this example case for understanding solve xxx before xxx?

In reply to UVM_LOVE:

You need many more randomizations.

See Why dist constraint doesnt produce exact solution? | Verification Academy