Unexpected Output during Shift Operation

SystemVerilog
,
1 

module  top_tb ;
  
 parameter  bit  signed [ 3 : 0 ] bs_3_0 =  7 ; 

 parameter  logic  signed [ 9 : 0 ] ls_9_0 = 20 ;

 initial  begin
   
    $display("%0d_%0d_%0d" , bs_3_0 , ( bs_3_0  <<  1 ) , ( ( bs_3_0  <<  1 ) > 0  )  ) ;
   
    $display("%0d_%0d_%0d" , ls_9_0 , ( ls_9_0  <<  5 ) ,  ( ( ls_9_0  <<  5 ) > 0  )  ) ; 
    
   
 end  
  
endmodule

My confusion is Result of ONLY Shift Operation i.e ( bs_3_0 << 1 ) and ( ls_9_0 << 5 ) give correct output

But when used with Relational Operator the Output is unexpected .

I expected “0” in 2nd operation i.e

( ( bs_3_0 << 1 ) > 0 ) and ( ( ls_9_0 << 5 ) > 0 )

2

In reply to Have_A_Doubt:

This is because you are shifting a 32-bit signed value. Relational operators, just like arithmetic operators extend all the operands before applying the operation. Try displaying ( ls_9_0 << 5 ) + 0

3

In reply to dave_59:

Thanks for the explanation Dave .

Is there a way that Shift Operation ( ( bs_3_0 << 1 ) > 0 ) is performed with 4 - bits ?

i.e End result of ( ( bs_3_0 << 1 ) > 0 ) is 0

One way is ::


localparam  BS_3_0  =  (  bs_3_0  << 1  ) ;
 
localparam  LS_9_0  =  (  ls_9_0  << 5  ) ;

initial  begin
   
   $display("%0d_%0d_%0d" , bs_3_0 , ( bs_3_0  <<  1 ) , ( BS_3_0 > 0  ) )  ;
   
   $display("%0d_%0d_%0d" , ls_9_0 , ( ls_9_0  <<  5 ) ,  ( LS_9_0 > 0  )  )  ;
    
   
 end

Is there a concise way without declaring extra parameters ?

I don’t use Size cast of 4’() and 10’() since the parameters could be of any Size . Was looking for Generic Solution .

4

In reply to Have_A_Doubt:

Do not use 0. Use a signed 1-bit value

( bs_3_0  <<  1 ) > 1'sb0
5

In reply to dave_59:

This is because you are shifting a 32-bit signed value. Relational operators, just like arithmetic operators extend all the operands before applying the operation. Try displaying ( ls_9_0 << 5 ) + 0

Hi Dave.,
In the above reply u have mentioned shift operation is done on 32-bit signed value, But in Have_A_Doubt code he has assigned variable size as 4bit[3:0] and 10bit[9:0].Please clarify.

6

In reply to Yash_wanth12345:

What Dave meant in the following :: ( ( bs_3_0 << 1 ) > 0 )

As the Max size of the Operands is 32 - bit , each Operand is Sign Extended to 32 - bits .

Hence bs_3_0 is Sign Extended from 4-bits to 32-bits .
Therefore I Observed 0 initially as output