Unexpected BUGS in "array of interface" and "array of modport"

SystemVerilog
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1

In this code I tried to implement some attributes of system verilog INTERFACE which are array of interface and array of moport.If I run the following code with any of the defined mode I get some “Unconnected Interface Port” error.Please let me know what to change in this code to make it functioning.Any suggestion would be appreciated.Thank you.



`define array_of_interface

interface intf;
logic [3:0] a,b;
logic c_in;
logic c_out;
logic [3:0] sum;

modport add(
			input a,b,
			input c_in,
			output sum,
			output c_out
);

modport sub (
			input a,b,
			output sum,
			output c_out
);
endinterface 


//Array of modport 

`ifdef array_of_modport

module adder(intf.add i_bus);
assign {i_bus.c_out,i_bus.sum}=i_bus.a+i_bus.b+i_bus.c_in;
endmodule 

module subtractor(intf.sub i_bus);
  assign {i_bus.c_out,i_bus.sum}=i_bus.a-i_bus.b;
endmodule 

module top_design (
output [7:0] con_sum [1:0],
output [1:0] c_out [1:0],
intf.add MODPORT_ADD [1:0],
intf.sub MODPORT_SUB [1:0]
);

adder con_add0(MODPORT_ADD[0]);
subtractor con_sub0(MODPORT_SUB[0]);
adder con_add1(MODPORT_ADD[1]);
subtractor con_sub1(MODPORT_SUB[1]);
assign con_sum[0]={MODPORT_ADD[0].sum,MODPORT_ADD[1].sum};
assign con_sum[1]={MODPORT_SUB[0].sum,MODPORT_SUB[1].sum};
assign c_out[0]={MODPORT_ADD[0].c_out,MODPORT_ADD[1].c_out};
assign c_out[1]={MODPORT_SUB[0].c_out,MODPORT_SUB[1].c_out};
endmodule 

`endif

//Array of interface

`ifdef array_of_interface

module adder(intf.add i_bus);
assign {i_bus.c_out,i_bus.sum}=i_bus.a+i_bus.b+i_bus.c_in;
endmodule 

module subtractor(intf.sub i_bus);
  assign {i_bus.c_out,i_bus.sum}=i_bus.a-i_bus.b;
endmodule 

module top_design (
output [7:0] con_sum [1:0],
output [1:0] c_out [1:0],
intf INTF_INS [1:0]
);

adder con_add0(INTF_INS[0].add);
subtractor con_sub0(INTF_INS[0].sub);
adder con_add1(INTF_INS[1].add);
subtractor con_sub1(INTF_INS[1].sub);
assign con_sum[0]={INTF_INS[0].add.sum,INTF_INS[1].add.sum};
assign con_sum[1]={INTF_INS[0].sub.sum,INTF_INS[1].sub.sum};
assign c_out[0]={INTF_INS[0].add.c_out,INTF_INS[1].add.c_out};
assign c_out[1]={INTF_INS[0].sub.c_out,INTF_INS[1].sub.c_out};
endmodule 

`endif
2

Dont think interface can be left open like regular ports. you can try something like this - add dummy module with similar ports and connect design and dummy instances like below

module dummy( intf.add INTF_INS_ADD [1:0],
intf.sub INTF_INS_SUB [1:0] );
endmodule:dummy

module tb();
intf INTF_INS1:0;
logic [7:0] con_sum [1:0];
logic [1:0] c_out [1:0];

dummy i_dummy(INTF_INS.add[1:0], INTF_INS.sub);

top_design i_top_design (
,
,
INTF_INS.add,
INTF_INS.sub
);

endmodule:tb