Understanding Address decoding with Hex calculation

SystemVerilog
,
1

Please find the below stated code


localparam CTRLA_ADDRESS        = 32'h00;
localparam CFG_ADDRESS          = 32'h04;
   

generate genvar access_1;
      assign reg_access.ctrla = (psel & (paddr32 == CTRLA_ADDRESS)) ? 1'b1 : 1'b0;
      for (access_1=0; access_1<CFG_REG_LEN; access_1=access_1+1) begin: reg_access
         assign reg_access.cfg_data[access_1] = (psel & (paddr32 == CFG_ADDRESS + access_1*'h04)) ? 1'b1 : 1'b0;
      end
   endgenerate

How the address decoding is being done here ?

access_1 = 0 : LSB bit of the reg_access ie bing assigned to 1 when paddr32 is equivalent to CFG_ADDRESS which is 32’h04

access_1 = 1 " Second bit from the LSB being assigned to 1 when paddr32 is equivalent to [ 32’h04 + 'h04 ] ?

whether we can do something like this ?

32’h04 + 'h04 ??

Basically how the calculations being done here .