Understand a way to pass a transaction ID in a combinational design

SystemVerilog
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I am stuck in a situation.

Current Status : I have certain transactions being generated and driven to DUT. Now DUT is a combinational block (Eg. just a net assignment from input to output). There is no unique states/ids in the design which can help differentiate each transaction being driven to the design. My goal is to do a compare the output with the input while the transaction is driven to DUT and monitored in DUT in two seperate mailboxes. Currently- my code is first finishing the collection of transactions from the DUT and then checking with the collected inputs. But the goal is to do parallely

My Thought : To go about bringing parallel checking - I thought of inserting the input transaction into an associative array with a trans ID as its unique index and then compare with output transaction once it receives by matching it agains the index. Question comes here - how to determine that index ?

Can someone please share some of their ideas here.

PS : This is a simple System Verilog Test Bench.(No UVM anything as such being used)

2

In reply to kb646bits:

What ask does not make much sense. If your design is truly combinational, it needs to respond to asynchronous changes in its inputs and produce outputs based on a set of requirements. Your testbench needs to supply stimulus and check the outputs based on those requirements.

If you are imposing some notion of timing in your stimulus in the form of a transaction, your testbench needs to be aware of that timing when checking results. i.e. you have an adder, and the output needs to be valid some time after the input have been applied.