Usually we use underscore in literal numbers to make it easier to review.
When we use %h to print a very long vector, like 128bit vector or 1024bit vector, it is also a good idea to have some underscore between like each 32bit.
I don’t think we have a builtin way to do so in Systemverilog. We can write a loop for each print though.
Do you think this is an interesting enhancement in next revision of SystemVerilog. Just similar to $timeformat to control the %t.
In reply to robert.liu:
All enhancements are potentially interesting.
From my experience, enhancements to SystemVerilog should pass through this checklist to be viable
- Introduced with 100% backward compatibility with what is already implemented in tools. Otherwise exiting designs break, and people rarely want their tools changing from what already works. Adding new system tasks is easy; new syntax is not.
- Is interesting enough for use by a wide enough audience that motivates most tool vendors to implement. Otherwise divergence in supported features prevents adoption. What level of pain does the feature reduce.
- The feature proposal leave little room for ambiguity. Ambiguity leads to divergence in implementations, which prevents adoption. What would happen if I asked for underscores between every 33 bits?
I hope you can see where I’m going here. As we get started with the next revision, there will be many interesting requests, and there is only a finite amount of time to address them. So I’m hoping any request comes along with the above considerations written down for the committees to assess.